Yanwen (Julia) Fei is a technical advisor in the firm’s Electrical Patent Prosecution practice group. Ms. Fei has over a decade of engineering and research experience in the integrated circuit (IC) industry, which includes IC design, IC manufacturing and IC testing.
Prior to joining the firm, Ms. Fei was a technical specialist at an Alexandria, Virginia IP law firm, where she drafted and prosecuted patent applications in electrical arts. She has experience in various technologies which include processors, storage devices, wireless communication, switching devices, printing devices, LED lighting devices and controllers.
Ms. Fei was a Ph.D. candidate at Carnegie Mellon University doing research in IC design for manufacturing and testing. She established a product-based methodology for process-induced variation characterization. In addition, she developed techniques for industrial data analysis to extract process-induced variations, which utilized spatial and temporal frequency analysis and physical sensitivity analysis to decompose a convoluted wafer map into elemental process variation wafer maps. She also created new yield models based on industrial data showing that accurate yield prediction is achievable at early stages of IC design.
Ms. Fei gained industrial experience at Motorola, working as a device engineer, test engineer and product engineer at numerous wafer fabrication and testing facilities. Ms. Fei also worked for PDF Solutions as a summer intern and worked for Philips Semiconductor as an extern.
- Carnegie Mellon University (Ph.D. candidate)
- Electrical and Computer Engineering
- Tsinghua University, Beijing, China (M.S.)
- Tsinghua University, Beijing, China (B.S.)
- Electrical Engineering
- Y. Fei, P. Simon, W. Maly, “New Yield Models for DSM Manufacturing”, International Electron Devices Meeting, 2000, pp. 845 – 848.
- T. Vogels, T. Zanon, R, Desineni, R.D. Blanton, W. Maly, J.G. Brown, J.E. Nelson, Y. Fei, X. Huang, P. Gopalakrishnan, M. Mishra, V. Rovner, S. Tiwary, “Benchmarking Diagnosis Algorithms with a Diverse Set of IC Deformations”, International Test Conference, 2004, pp. 508 – 517.
- U.S. Patent No.7,348,594